Semiconductor devices continue to be scaled to smaller dimensions. The reduction in size of circuitry such as capacitors and dynamic random access memory (DRAM) bit cells, has prompted a need to integrate high dielectric constant materials into the fabrication of such devices. Barium strontium titanium oxide (BST) and similar materials are high dielectric constant (high-K) materials currently being used as part of this integration scheme.
The present inventors have recognized that at high temperatures, BST chemical vapor deposition processes are mass transfer limited, where species react as soon as they land on the substrate surface on which they are being deposited. In the mass transfer limited process, there is sufficient energy in the system such that reaction takes place immediately upon components contacting an area for nucleation and growth. Such immediate reaction results in poor step coverage of the deposited film. In an attempt to obviate the negative effects of mass transfer limited reactions, the present inventors have considered reducing temperature to move the process from a mass-transfer-limited regime to a reaction-limited regime. In the reaction-limited regime the reaction occurs slowly enough such that the species can diffuse across the surface of a feature before the reaction occurs, thereby producing improved step coverage. However, operating at a low temperature results in a lower deposition rate of the film and poor crystallinity of the film. In addition, operating at low temperatures results in impurities, such as carbon, being trapped in the deposited film. One method of overcoming the problems with poor crystallinity associated with low temperature deposition processes includes removing the wafer from the chamber and annealing it at a high temperature. This can recrystallize the BST film thereby achieving desired electrical properties. However, this additional processing step introduces new integration problems.
Shown in FIG. 1 is an illustration of a semiconductor device substrate 10 having a capacitor dielectric 124 overlying a bottom electrode layer or post 122. As illustrated in FIG. 1, the step coverage of the capacitor dielectric 124 is such that the sidewall thickness is less than the thickness of the film overlying the top portions of electrode post 124, due to mass transfer limited deposition. Non-uniform thickness of the dielectric overlying the capacitor electrode can produce problems with leakage in areas where the dielectric is too thin. Attempting to overcome the leakage problems by increasing the overall dielectric thickness reduces the capacitance of the device, and is thus undesirable.
In view of the foregoing, it is desirable to deposit films having superior quality in semiconductor devices.